1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device having a memory cell portion.
2. Description of the Background Art
Because of the increase in integration degree of semiconductor devices, and because of the miniaturization of memory cells particularly in semiconductor storage devices, it is becoming difficult to form contacts between interconnections without causing short circuits.
In order to form contacts without causing short circuits with interconnections, a method called self-alignment is often adopted. Contacts formed by the self-alignment technique are called self-aligned contacts (SAC).
In memory cell portions, in order to increase short circuits margin, it is common to form contacts by SAC etching using etching masks with large opening ratios, called bar-type or line-type, instead of hole-shaped ones, which is followed by chemical mechanical polishing (CMP).
For example, Japanese Patent Application Laid-Open No. 6-216333 (1994: Column 4, FIGS. 3 and 4) describes a method for forming contacts using self-alignment technique.
As described in the patent document cited above, transistors in the memory cell portion and transistors in the peripheral circuit portion are formed simultaneously, and therefore the transistors in the peripheral circuit portion undergo a thermal process for improving the burying characteristics of interlayer insulating film in the memory cell portion and a thermal process for improving the refresh characteristics, which causes thermal diffusion of impurities in the source/drain regions of transistors in the peripheral circuit portion that require impurities at high concentration, possibly reducing punch-through margin of the transistors in the peripheral circuit portion.
Furthermore, while SAC etching was conventionally not applied to peripheral circuit portions, the demand to enhance the degree of integration is now requiring the technique to be applied also to peripheral circuit portions, and further miniaturization of semiconductor devices is now necessitating ensuring short circuits margin and enhancing current driving capability also in the peripheral circuit portions.